This invention relates generally to semiconductor memories, and more specifically, to sense amplifiers used in semiconductor memories.
Sense amplifiers are used in conjunction with memories such as a static random access memory array (SRAM). Sense amplifiers function to detect when complementary bit lines in a memory array exhibit a voltage transition in response to column and row decoding and a sense enable signal. In an SRAM, there is a need to amplify and decode signals provided via columns of memory cells. Transistor pass gates are frequently used to perform column decoding. However, the amplification and decoding of such signals needs to be done with minimized ohmic losses in transistor pass gates. A static RAM bit line differential bit line signal develops in a manner that increases with time. Hence, whenever a differential signal is conducted by a pass gate, there is detriment to the differential signal that may be characterized in terms of either a time delay or a reduction in its magnitude. In the art, these two characterizations are often referred to as an RC (resistance multiplied by capacitance) time delay or an RC delay. Pass devices for connecting bit lines to data lines tend to delay the passage of a differential signal due to the RC time constant. There is typically a trade between improving the timeliness or magnitude of bit line and data line signal levels versus device count and amplifier reliability. In general, amplifier reliability refers to the collective ability of all amplifiers in a memory to guarantee an accurate signal given known offsets and error voltages.
An objective of memory sense amplifiers is to avoid drawing excess charge from a bit line subsequent to clocking the sense amplifier. One technique to accomplish this objective is to use a cascode pair of transistors directly connected to the bit lines. A disadvantage of the cascode pair of transistors is that the cascode pair delivers a fairly small signal, as compared with the full VCC power supply value, to the local data lines. As a result, driving a global data line with the small signal is problematic. Another technique to accomplish this objective is to turn off the column decoders subsequent to the clocking of the sense amplifier, and thereby avoid pulling current from the bit lines. This technique adds circuit complexity and timing criticality to the design.
It is desirable to sense a data signal with an amplifier containing a cross-differential coupled pair of transistors. The timing of turn-on of the sense amplifier is critical. One measure of a sense amplifier""s quality is the minimum differential signal that the sense amplifier is able to accurately sense. An objective in sense amplifier design is to provide the maximum differential signal to the difference in gate-to-source drive (delta VGS) of the differential cross-coupled pair. Another critical design parameter associated with sense amplifiers is associated with the operation of a differential cross-coupled pair of transistors. The design parameter involves insuring that the difference in gate-to-source drives is greater than zero at the time the pair is clocked. If not, the output signal may not be accurate. In general, prior sense amplifiers have involved a trade-off between speed, size and power consumption.